Embodiments of the present invention relate generally to a method and apparatus for the protection of an electronic circuit's power pad and input/output circuitry from electrostatic discharge (ESD).
Current designs of ESD protection circuits such as the one shown in prior art FIG. 1 offer protection from ESD using techniques that trigger the protective action based on the rapid voltage transition of a voltage bus, typically a Vdd bus. The ESD protective circuit acts to shunt the ESD biased Vdd bus to the Vss bus, or ground, when the rate of increase in voltage of the Vdd bus satisfies predetermined rate criteria. A common implementation of a rate detection circuit utilizes a resistor and capacitor (RC) combination as shown in FIG. 1, where resistor R and capacitor C act to maintain node B2 either high or low, based on the time constant of the RC combination. A high node B2 acts to gate (turn-on) the NMOS transistor B6 and shunt the Vdd bus to the Vss bus and a low node B2 acts to turn-off NMOS transistor B6. As shown in FIG. 2, a limitation of the existing RC combination scheme is that the use of the resistor R causes the voltage at node B2 to decay at a rate that effectively limits the level to which the Vdd bus voltage can be lowered.
Also, the ESD protective circuit implemented in FIG. 1 is not configured entirely inside the power pad or input/output (I/O) pads of the respective circuits but instead are comprised of circuit elements located external to the power or (I/O) pads. This requires the cooperation of circuit elements located inside the power pad or I/O pads with elements outside the respective pads thereby creating undesirable complexity and potential reliability issues.
It is desirable to provide a circuit that discharges an electrostatic biased voltage in a power pad or input/output pad to voltage levels lower than levels at which existing ESD protection circuits can discharge ESD and in a time frame that prevents circuit damage from occurring. Further, it is desirable for such an ESD protection circuit to be located entirely inside the power pad or input/output (I/O) pad and not require specially designed ESD circuitry located outside the power pad or I/O pad.